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application note low power low voltage modem analog front-end stlc7550 AN930/0298 by alain borg, fabien friess contents i overview ........................................................... 2 ii compatibility with stlc7546 ........................................ 2 iii clock generator .................................................. 3 iii.1 clock generator modes . . . . ....................................... 3 iii.2 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . ......................... 4 iii.2.1 third overtone crystal oscillator . . . . . . . . . . . . .............................. 4 iii.2.2 fundamental mode crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . ................ 5 iv serial interface ................................................... 6 iv.1 control mode. . . . . . . . . . . . . . . . . . . . . . . . . . . ........................... 6 iv.2 master/slave mode. . . . ............................................. 7 iv.3 ts pin. ........................................................... ... 7 iv.4 reset and powerdown . . . . . . . . . . . . . . . . . . . . . . . ...................... 8 v digital filters ..................................................... 8 v.1 transmit d/a section . .............................................. 8 v.1.1 architecture. .......................................................... 8 v.1.2 frequency response . . . . . . . . . . . . . . . . . . . . . . ............................. 8 v.2 receive a/d section. . . . . . . . . ........................................ 8 vi line interface ..................................................... 11 vi.1 duplexor . . . . ...................................................... 11 vi.1.1 differential duplexor . . . . ................................................ 11 vi.1.2 low cost daa using a 1:1 transformer . . . . . . . ............................. 15 vi.1.3 low cost daa using a 1:1.414 transformer . . . . . . . . . . . . . . . . . . . . . . . .......... 18 vi.1.4 low cost daa for complex impedances . . . . . . . ............................. 19 vi.2 current driver . . . . ................................................ 22 iv.2.1 ring detect . .......................................................... 22 iv.2.2 protection devices . .................................................... 22 iv.2.3 hook switch . . . . ...................................................... 22 vii application ........................................................ 23 viii performances ..................................................... 24 viii.1 adc converter . .................................................... 24 viii.2 dac converter . .................................................... 24 viii.3 daa characteristics . .............................................. 26 1/27
analog modulator 2nd order modulator low-pass (0.425 x sampling frequency) hc0 out+ out- v cm v refn v refp in+ in- (0 + 6db in diff. input) dac 1 bit first order differential switched capacitor filter low-pass (0.425 x sampling frequency) serial ports and control register atten. 0db/+6db/ infinite m/s fs sclk dout din clock generator xtalin xtalout agnd2 agnd1 av dd dv dd dgnd stlc7550 reset pwrdwn 38 16 6 5 9 8 31 20 29 37 36 30 19 18 28 27 15 ts 7 mcm 39 hc1 14 17 4 3 42 41 tstd1 40 auxin+ auxin- 26 25 mux AN930-01.eps figure 1 i - overview stlc7550 is a single chip analog-front-end (afe) designed to implement modems up to 56kbps. it has been designed for host processing applica- tion in which the modulation software (v.34 , 56kbps)is performedby the main applicationproc- essor : pentium,risc or dsp as well as pc modem with dsp. the main target of this device is stand alone appli- cations as hand-held pc (hpc), personal digital assistants (pda), webphone s, network com- puter, set top boxes for digital television (satellite and cable). to comply with such applications stlc7550 is powered nominally at 3v. 30mw maximum power dissipation is well suited for battery operations. in caseof batterylow, stlc7550 will continueto work even at a 2.7v level. stlc7550 provides clock generator for all sam- pling frequencies requested for v.34bis and 56kbps applications. this afe can also be used for pc mother boards or add-ons cards or stand alone modems. it is compatible with previous stlc7546 designs and can be powered at 5v. ii - compatibility with stlc7546 stlc7550 has been designed to be compatible with stlc7546 application. additional features in stlc7550 are described hereafter. - a master/slave mode to allow a dual codec structure, - an integrated programmable frequency gener- ator that makes stlc7550 codec able to gener- ate all v.34bis and 56kbpssampling frequencies. (see chapter iii - clock generator), - an on-chip crystal oscillator, - a low power consumption of 30mw @ 3v. stlc7550 has been targeted for 3v application, however it has a power supply range of 2.7 to 5.5 that allows it to work also in previous 5v (or 3v) stlc7546 designs, - stand-by mode power consumption less than 3 m w @3v. figure 2 gives the implementation of stlc7550as a stlc7546 codec. note that stlc7550 m/s pin must be connected tovdd, and that there is no compatibility for test modes (stlc7546 test pins and registers are used for additional features in stlc7550). stlc7550 application note 2/27
3 4 6 7 8 9 16 17 18 19 20 27 28 30 36 37 38 41 31 39 42 40 stlc7550 (used as stlc7546) mcm (vc1) xtalout (vc2) xtalin (mclk) din dout fs sclk reset pwrdwn tstd1 m/s (tsta) ts (tstd2) dgnd agnd1 agnd2 in+ in- out+ out- v refp v cm v refn names within brackets correspond to stlc7546 pin names v dd 10 m f 10 m f 100nf 10 m f to daa to digital controler 100nf 100nf 529 dv dd av dd 22 m f 100nf v dd 22 m f 100nf v dd 14 15 hc1 hc0 2.2nf 2.2nf 1.2k w 1.2k w 100k w 25 auxin+ 2.2nf 1.2k w 26 auxin- 2.2nf 1.2k w v cm v cm v cm v cm a n930-02.e ps figure 2 : implementation of stlc7550 as a stlc7546 codec ii - compatibility with stlc7546 (continued) iii - clock generator iii.1 - clock generator modes figure 3 gives the clock generatorarchitecture.depending on the mcm input state, two modes are available (see table 1). table 1 : clock generator modes mcm xtalin xtalout sclk fs description 0 xtalin pin should be driven by an fsx over clock, with fs the required sampling frequency. not used. should be left open, or can be connected to ground for compatibility with stlc7546. xtalin xtalin/ over stlc7546 mode. sampling frequencies are generated externally. 1 connected to a crystal (e.g. 36.864mhz) xtalin/ (mxq) xtalin/ (overxmxq) all v.34 and 56kbps frequencies are generated internally by stlc7550, by programming over, m and q registers. stlc7550 application note 3/27
iii.2 - crystal oscillator when pin mcm is set to 1, the master clock is provided by a crystal oscillator connected between the xtalin and xtalout pins. the nominal frequency of the oscillator is 36.864mhz. at this frequency, both third overtone and fundamental mode crystals are available. iii.2.1 - third overtone crystal oscillator figure 4 gives the schematic for an oscillator using a 36.864mhz third overtone crystal with a load capacitance c l of 10pf. the design is a 'pierce' structure with an additional inductor at the output side for right start-up at the third overtone. bit 3-4-5 internal sampling m/s sync fs sclk (oclk) % over xtalin (mclk) xtalout m q mcm cont. reg. : bit 8-9-10-11-12-13 v dd AN930-03.eps figure 3 : clock generator stlc7550 xtalout xtalin fq = 36.864mhz third overtone c l = 10pf 89 c1 27pf l1 1.2 m h c2 10nf c3 10pf cp 10pf cp 10pf rsb 10m w cp : parasitic capacitance (pcb, ic input) AN930-04.eps figure 4 : oscillator schematic for 3rd harmonic mode crystals. iii - clock generator (continued) rsb is optional. this resistor influences the stand by mode current consumption isb : without rsb isb 15 m a with rsb = 10m w isb 1 m a. in order to complete the start-up condition (i.e. at nominal frequency the loop gain has a phase angle of 0 degrees and a module greater than 1), feedback components must provide a -180 degrees phase shift to the stlc7550 inverter action : - 1st rc cell: output r of inverter / total output capacitance, - 2ndrc cell:serialr ofcrystal/ totalinputcapacitance. when the oscillator is running, current is exchanged through the crystal between its load capacitors, with always inverted phase voltages across them. when a serial resonant crystal is used in such an oscillator, resulting frequency is always greater than target frequency, and a too high capacitor value should be necessary to converge. for this range of frequencies (35 to 50mhz), a third overtone crystal specified with parallel 10pf load is suggested.then, the basis capacitor's values of the apierceo design are 20pf each; if crystal is specified with higher c l , resulting capacitors can become too high for the oscillator starting up. if an overtone crystal is used in a classic apierceo structure without inductor, re- sulting frequency will be around the fundamental. if an inductive reactance is forced lower than the capacitance's one for the fundamental (see figure 5), it cancels the start up condition of the oscillator (+90 instead of -90 into a feedback cell). for the third harmonic's frequency of the crystal, using properties of the lc cell, inductor's impedance is lower than capacitance's one. then, resulting re- actance is forced by the capacitance, and the goal is reached. 12 c1 c3 l1 output r serial r of xtal c2 - 180 -90 near - 90 for h3 (near + 90 for fund.) r AN930-05.eps figure 5 : third overtone oscillator simplified schematic stlc7550 application note 4/27
computing of application's schematic values (see figure 4) the crystal is supposed to be specified as: 36.864mhz, third overtone, cl = 10pf. input capacitance of the oscillator has to be twice cl, therefore 20pf made by : - parasitic value cp from the chip and from the board layout, supposed to be about 10pf - capacitor c3 (10pf) on the output side, it is necessary to take care of the inductor to computethe value of c2. the l1,c1 cell preventsthe crystal to oscillate at its fundamen- tal frequency. the cell cut-off frequency (fc) is typically set near 2/3 of the third overtone : ( 1 ) f c = 2 3 ? f q with f c = 1 2 p `````````````` l1 ? ( c1 + cp ) fc value is not critical. a value too close to f q is not recommended, becauseof the too high impedance reached which can open the feedback network of the oscillator. the l1,c1 cell is also optimized to balanceequiva- lent capacitance at both crystal pins at f q . for this purpose,at thirdovertone frequency,the l1,c1 cell shouldbe equivalentto the c3 capacitor. this gives the following condition : z l, c = z c3 with z c3 = 1 j ( c 3 + c p ) ? w ' and z l, c = l1 M M c1 = jl1 ? w 1 - l 1 ? ( c 1 + c p ) ? w 2 using relation (1) with w q =2 p ? f q , this condition can be reduced to : ( 2 ) c 1 + c p = c 3 + c p 1 - ( 2 3 ) 2 = c 3 + c p 0.55 = 2cl the closest standard value are : c3 = 10pf c1 = 27pf l1 = 1.2 m h bypass capacitor's value is not critical (10nf to 100nf). c2=10nf the final frequency will depend on the evaluation of parasitic capacitors. an accuracy of 10ppm is possible. note that all oscillator components should be mounted close to the codec with direct traces to the xtalin, and xtalout pins. specifications for components values of stlc7550 third overtone oscillator are : crystal : - a serial resistor r s 50 w . if higher, oscillator start- up may be compromised. - third overtone, parallel resonant mode - frequency tolerance: 50ppm (frequency and temperature) - a load capacitance cl around 10pf. if cl is higher, resulting capacitors can become too high for the oscillator starting up. inductor : - l1 value : 10% - dc resistance < 0.3 w - wirewound inductor recommanded capacitors : c1,c2 : 10% iii.2.2 - fundamental mode crystal oscillator figure 6 gives the apierceo structure for an os- cillator using a 36.864mhz fundamental mode crystal. c1 + cp value is chosen as two times the crystal load capacitance cl. crystal specifications are : - a serial resistor r s 50 w . if higher, oscillator start- up may be compromised. - fundamental, parallel resonant mode - frequency tolerance : 50ppm (frequency and temperature) - a load capacitance cl (10pf type for this fre- quency crystal range). if cl is higher, resulting capacitors can become too high for the oscillator starting up. iii - clock generator (continued) stlc7550 xtalout xtalin fundamental mode 89 c1 = 2cl c1= 2cl 10pf 10pf AN930-06.eps figure 6 : oscillator schematic for fundamental mode crystals. stlc7550 application note 5/27
sampling period, (64, 96, 128, 160 or 192) sclk 1/2 sampling period (only if control mode selected) data word input (15 bits) 0 d15 d1 d0 d15 data word input (15 bits) data word output (16 bits) d15 d0 d15 data word output (16 bits) data word input (15 bits) 1 d15 d1 d0 d15 data word input (15 bits) d0 control word (16 bits) data word output (16 bits) d15 d15 data word output (16 bits) d0 d15 control word (16 bits) d0 d15 fs txdi txdo txdi txdo hc1=0 hc0=0 d0 data word input (16 bits) txdi d15 d15 data word input (16 bits) d0 data word output (16 bits) txdo d15 d15 data word output (16 bits) d0 data word input (16 bits) txdi d15 d15 data word input (16 bits) d0 data word output (16 bits) txdo d15 d15 data word output (16 bits) control word (16 bits) d0 d15 control word (16 bits) d0 d15 hc1=0 hc0=1 hc1=1 hc0=x AN930-07.eps figure 7 : chronogram of serial interface for data and control modes (pin ts = 0). iv - serial interface iv.1 - control mode stlc7550 has only one 16-bit control register which makes the codec easy to program. the codec presents two different modes : - a data mode whereonly dataare exchangedin the frame (data word input and data word output). - a control mode where data are followed by con- trol words for register access (control word to program the control register, and register word to read the register state). the mode (data or control) can be selected either by software or hardware (see figure 7) : - software : hc1 = hc0 = 0 and lsb of data word input select the mode : - lsb = 0 : data mode lsb = 1 : control mode - hardware : hc0 = 1 and hc1 select the mode : - hc1 = 0 : data mode hc1 = 1 : control mode note that in software control mode, data word input is on 15 bits only. after the codec has been configured it can be convenient to switch to the hardware data mode (hc0 = 1, hc1 = 0) to get a full 16 bits data exchange. stlc7550 application note 6/27
iv.2 - master/slave mode digital interface can be synchronized by either stlc7550 (master mode) or by an other device (slave mode). - in master mode, the codec generates the fs signal (fs pin is an output), with half period extra synchronizationpulse for control frame if needed. - in slave mode, the codec receives the synchro- nization signal fs on the pin fs (set as input). half period extra synchronizationpulse for control frame should be also present on fs input when needed. however since codec programming re- quires only one frame (only one control register), the 1/2 sampling period pulse is not mandatory. in that case programmingwill be done on the next fs pulse and only one data sample will be lost. iv.3 - ts pin when ts = 0 data are assigned to the first 16 bits after falling edge of fs (7546 mode)otherwise data are in bits 17 to 32. (note that the casem/s = 1 with ts = 1 is reserved for life-test). this feature allows dual codec application. an example is given on figure 8, and the resultingchronogramof the serial interface is given on figure 9. note : when programmingeither codec in software mode, both codecs should be in fact programmed at the same time. as fs is the same for both, the secondarypulse canbe interpretedas a mainpulse by the codec that is not being programmed with a complete loss of synchronisation. in hardware mode this problem is not presentbecause hc0 and hc1 control both codecs at the same time. iv - serial interface (continued) sampling period, (64, 96, 128, 160 or 192) sclk 1/2 sampling period (only if control mode selected) fs data word input (15 bits) 1 txdi d15 d1 d0 data word output (16 bits) txdo d15 d0 slave codec data word output (16 bits) data word input (15 bits) 1 d1 d0 d15 d0 master codec register word (16 bits) d15 d0 slave codec register word (16 bits) d15 d0 master codec control word (16 bits) d15 d0 control word (16 bits) d15 d0 AN930-09.eps figure 9 : example of serial interface chronogram for dual codec application (hc0 = 0, hc1 = 0) sclk fs din dout bclk fs do di xtalin m/s mcm stlc7550 processor v dd f q = 36.864mhz (or other frequency) sclk fs din dout hc0 m/s mcm stlc7550 gnd hc0 xtalin gnd v dd ts gnd hc1 hc1 master codec ts v dd slave codec a n930-08.eps figure 8 : dual codec application stlc7550 application note 7/27
device active reset state 160 x mclk reset fs powerdown state operation resume over x mclk pwrdwn fs AN930-10.eps figure 10 : reset and powerdown exit time iv.4 - reset and powerdown (see figure 10) serial interface table 2 : serial interface state during reset and powerdown master mode (m/s = 1) slave mode (m/s = 0) mcm = 1 mcm = 0 mcm = 1 mcm = 0 sclk v dd mclk v dd mclk fs gnd gnd hi z hi z dout hi z hi z hi z hi z control register whenreset pin isset to0,thecodecissetto thestate given intable 3.in powerdown mode(pwrdwn = 0), no change is done on the configuration register, and so the previous programming is preserved. table 3 : reset state bits reset value reset state d0 0 - d1 0 main receive input d2 0 0db receive gain d3 0 over = 160 d4 0 d5 0 d6 0 infinite transmit attenuation d7 0 d8 1 m=4 d12 0 d13 0 d9 1 q=6 d10 0 d11 0 d14 0 no test mode d15 0 iv - serial interface (continued) low pass filter iir + fir sinx/x compensation 2nd order modulator noise shaper single pole analog low pass filter out din 0.425 x sampling frequency f c = oclk 2x p x10 AN930-11.eps figure 11 v - transmit and receive filter stages v.1 - transmit d/a section v.1.1 - architecture (see figure 11) the complete d/a section is composed of the following filter stages : - transmit low pass filter (interpolating filter) with com- bination of fir + iir as well sinx/x compensation, - digital second order noise shaper, - single pole analog low pass filter. v.1.2 - frequency response in band frequency response (0-5khz) figures 12 and 13 show the transmit frequency response of the complete transmit channel. the measurement have been done with a rodhe &schwarz audioanalyzer2hz-300khzupd. the sampling frequency is 9.6khz and oversam- pling ratio is 160. figure 12 is the frequency re- sponse with a accurate scale which shows that thanks to the sinx/x compensation, the frequency responseis flat in the frequency band [0-0.425x fs]. figure 13 shows the filter performances. out of band spectrum figure 14 gives the output signal measured at the differential outputs out+/out-. the total noise level is this frequency band is -27dbv. in order to comply which the out of band noise specification, measured on the phone line, an external second order continuous time filter is necessary. figure 15 shows the phone line spectrum measured with our demoboard using the filter characteristics de- scribed on chapter vi of this application note. the total noise level in the 100khz band is -63dbv. v.2 - receive a/d section (see figure 16) the a/d channel performs the decimation function using 2 filters, one fir and one iir. the cut-off frequency is 0.425 x sampling frequency. stlc7550 application note 8/27
AN930-12.pcx figure 12 : frequency response (0-5khz) flat thanks to sinx/x compensation v - transmit and receive filter stages (continued) AN930-13.pcx figure 13 : tx filter efficiency AN930-14.pcx figure 14 : out of band signal at the codec output stlc7550 application note 9/27
a n930-15.p cx figure 15 : out of band signal on the phone line v - transmit and receive filter stages (continued) AN930-16.pcx figure 16 : ad section filter (over = 160) stlc7550 application note 10/27
vi - line interface stlc7550 is targeted for v.34bis standard and 56kbpsnewstandardandforlow-powerapplication. line interface has to present : - good performances to allow high speed commu- nication, - a supply around 3v only, - small size to allow the modem to fit in portable applications for which low-power solutions are usually dedicated. an overview of the proposed modem line interface isshown on figure 17. thestlc7550 transmitand receive signals from the phone line via a duplexor (that isolates modem from phone line, filters and amplifies signal) and a bridge (to allow the mo- dem to work even tip and ring are inverted).then the line is taken with a on hook/off hook switch, and by driving a constant current (current driver block). a ring detect block signals to the digital controllervia the ring signal incoming calls. the different blocks are detailed hereafter. vi.1 - duplexor vi.1.1 - differential duplexor this duplexor is also called hybrid for it interfaces the 2-wire bi-directional phone line in two separate differential and unidirectional lines to the codec (transmit and receive). a differential duplexor for the modem part is given on figure 18. hybrid performances are mainly depending on a good impedance matching with the phone line and a good transmit rejectionon the receiveinput (loss). in+ out- current driver protection duplexor transmit out+ in- receive tip ring stlc7550 bridge hook switch off-hook ring detect ring-in AN930-17.eps figure 17 : line interface overview out- out+ in- in+ s t l c 7 5 5 0 c2 2.2nf 4.7 m f/50v to the phone line midcom 671-8332 zo/2 160 w zo/2 160 w r8 13k w r8 13k w r6 22k w r7 22k w r7 22k w r6 22k w r5 1.2k w r5 1.2k w r3 22k w r4 15k w r3 22k w r2 20k w r1 27k w r1 27k w c1 330nf c1 330nf r2 20k w c6 2.2nf npo c7 2.2nf npo c4 100pf c5 100pf v cm f c = 19.6khz 100nf av dd agnd 11 4 agnd x4 ts924 pins 1-7-8-14 pins 3-5-10-12 pins 2-6-9-13 : as close as possible to stlc7550 pins * * * c3 680pf 37 36 27 28 ** ** : optional - see note p 10/18 agnd AN930-18.eps figure 18 : differential duplexor stlc7550 application note 11/27
vi - line interface (continued) ideal transformer zline zo tip ring rs m rp duplexor tip ring AN930-19.eps figure 19 : line interface equivalent model a. phone line impedance matching impedancemismatches betweenline and daacause reflections and interference between transmit and receivesignalsgiving echoesthatlimit modemspeed. the impedance matching is related to the phone line impedance (zline) - that depends on the country, line length, and the signal frequency. the following sche- matics are targeted for zline = 600 w . see paragraph vi.1.4 for an example with complex impedance. figure 19 shows the equivalent model of a line interface, where zo is the duplexor equivalent im- pedance, r p and r s the transformer resistance, and zline the phone line impedance. the impedance matching condition is : r p +z o /m 2 +r s /m 2 = zline [1] application : the midcom 671-8332 transformer used gives the following performances : -r p = 155 w ,r s = 150 w - turns ratio m = 1 1% - longitudinal balance : 40db min. - total harmonic distortion : 82db - insertion loss : 3.0db typ. zline = 600 w [1] = z o = (zline-rp) . m 2 -r s = 295 w impedance recommended by midcom is 316 w . we take z o /2 = 160 w . **note : the capacitor c2 is used to add a third external pole for dac-channelnoise rejection. nev- ertheless, it can increase electrical echo on receive section. it is dependenton the phone line type. b. transmit rejection for full duplex communication a transmit signal rejection on the receive part is made by resistor r1 and r2. in that way, only the incoming phone line signal is present on the receive output. the loss of transmit signal is given by (see figure 20) : loss = v receive v transmit ( no signal received ) [2] = 20 ? log ? ? ? z eq z eq + z o ? r1 r1 + r2 - r2 r1 + r2 ? ? ? with zeq being the equivalent impedance of the phone line impedance seen from the secondary of the transformer. maximum loss is achieved when : z eq z eq + z0 = r2 r1 [3] application : r2 = 20k w , zo = 320 w z eq =r s +rp ? m 2 + zline.m 2 = 905 w [3] => r1 = (z eq +z0) ? r2/z eq = 27.07k w . we take r1 = 27k w . [2] => loss = -59db (theoreticalvalue, resistor values should be certified at 1% for good performances). c1 = 330nf. c1, r1 improves the low frequency response. these values depend on the transfer function of the transformer. filter transfer function made by c1, r1 must compensate for the loss in trans- former at low frequencies. if a compensation is not needed, the capacitor c1 can be suppressed. r1 27k w zo/2 160 w r2 20k w receive transmit signal rs/2 rp/2 . m 2 zline/2 . m 2 zeq/2 zo/2 160 w line signal 330nf c1 AN930-20.eps figure 20 : transmit rejection simplified ac schematic stlc7550 application note 12/27
vi - line interface (continued) c. transmit filter (see figure 21) atwo-pole continuoustime external filter must follow the output pin in order to remove quantizationnoise. the filter characteristics are : transfer function with : h = g t ? 1 1 + 2 ? x ? s + s 2 with s = j w 2 p ? f c dc gain : gt = r6 r8 overvoltage factor : x = 1 2 ? ? ? ? `` ` r7 r6 + `` ` r6 r7 + ```````` r6 ? r7 r8 ? ? ? ? ```` ` c4 2 ? c3 cutoff frequency : f c = 1 2 p ``` r 7 ? r 6 ? c 4 ? 2 ? c 3 with f c > 2 ? f s [4] f c must be at least twice the value of the sampling frequency. the filter also amplifies (with a gain g t ) the trans- mit signal to compensate the loss (l t ) due to the divider made of resistor z0 and equivalent line impedance z eq . the gain condition that makes the codec maximum output level a c to match with maximum phone line level a l is : a c ? l t ? g t = m ? a l with g t = r 6 r 8 and l t = z line z o + z eq [5] for low-power application,op-amp supply is limited to 3v and can be a limitation. it is advised to use rail to rail op-amp dedicated to 3v application. op-amp should never saturate, i.e. the op-amp output signal peak-to-peak level should lie within the supply range : a c ? g t <3v [6] application dtmf level is considered as the highest level to be transmitted. levels used in this application are : - high group tone level : -9dbv + 2/-2.5 (1v pp ) - low group tone level : -11dbv + 2.5/-2 (0.80v pp ) - the level ofthetonein thehighgroupmust be1db to 4db higher than the level of the tone in the low group. in consequencemaximum dtmf signal level is within 1.38 and 2.32v pp . the maximum phone line level is set to 2.2v (corresponding to a 0dbm single tone). 2 ? a l = 2.2v pp (2 ? a l becauseof differentialstructure) ? a l = 1.1v pp z0 = 320 w , zline = 600 w ,z eq = 905 w , [5] gives l t = 0.490, a c =1.25v, m = 1 [5] gives g t =m ? a l /(a c ? l t ) = 1.795 = +5db choosing r6 = 22k w gives r8 = 13k w (stlc7550 minimum load is 10k w ) and g t =2 [6] a c ? g t = 2.5v pp < 3v op-amp are not saturated note : the maximum line level during v.34 commu- nication is around 1.2v pp . this gives a maximum signal level on codec output pin around 0.6v pp [1.2/(2 ? g t ? l t )] that gives a good dynamic with no distortion. sampling frequency : 9.6khz gives f c # 19.2khz choosing r7 = 22k w , c3 = 680pf and c4 = 100pf, [4] gives f c = 19.6khz r8 13k w r6 22k w r7 22k w c4 100pf 2 x 680pf 2 x c3 v cm out- out+ s t l c 7 5 5 0 r8 13k w r8 13k w r6 22k w r7 22k w r7 22k w r6 22k w c4 100pf c5 100pf v cm f c = 19.6khz c3 680pf 37 36 * ideal transformer 2x z0/2 160 w r s /2 r p /2 . m2 zline/2 . m2 z eq /2 m line * ai a c g t l t m a n930-21.e ps figure 21 : transmit filter stlc7550 application note 13/27
vi - line interface (continued) d. receive amplifier receive amplifier compensate with a gain g r : - the loss l r due to the resistor r1 and r2 divider, - the loss l t due to the transformer, composed by the resistor z o and the transformer impedance r s +rp ? m2 the gain condition that makes the maximum line level a l match with the maximum stlc7550 input level a s is : application : m=1 maximum line level : 0dbm, 2 ? a l = 0dbm = 2.2v pp ,a l = 1.1v pp , r1 = 27k w , r2 = 20k w ,l r = 0.57, z o = 320 w ,r s = 150 w , rp = 155 w ,l t = 0.512, a s =1.25v pp g r =a s /(a l ? l r ? l t ) = 3.89 = 11.8db we take r3 = 22k w and r4 = 15k w ,gives g r = 3.93 = +11.90db. note : the maximum line level during v.34 commu- nication is around 1.2v pp . this gives a maximum signal level on codec input pin around 0.68v pp [(1.2 /2). l r ? l t ? g r )] that gives a good dynamic with no distortion. resistor r4 has also the function of balancing signal tp1rx+ and tp1rx- to improve symmetry. note : va is the average voltage between v out + and vout- that represents the output asymmetry. in ideal conditions it should be equal to 0. the single pole anti-aliasingfilter (r5, c6) removes high frequency noises. c6 must be put as close as possible to the chip. the cut-off frequency must be lower than one half of the oversampling frequency (i.e. lower than 460khz). tp1rx- tp1rx+ 27 28 stlc7550 r5 1.2k w r5 1.2k w r3 22k w r4 15k w r3 22k w c6 2.2nf npo c7 2.2nf npo r5 1.2k w r3 22k w r4/2 15k w c6 2.2nf va r2 20k w r1 27k w zo/2 rp/2 . m 2 rs/2 v out+ v in+ 2x m line a l * l t m lr gr as * ideal transformer agnd AN930-22.eps figure 22 : receive amplifier stlc7550 application note 14/27
out- out+ in- in+ s t l c 7 5 5 0 c0 2.2nf 4.7 m f/50v phone line midcom 671-8332 zo 320 w r1 13k w r1 13k w r3 22k w r2 22k w r2 22k w 1.2k w r7 10k w c1 100pf f c = 19.6khz 100nf av dd agnd 8 agnd x2 ts922 pins 1-7 pins 3-5 pins 2-6 : as close as possible to stlc7550 pins * c2 680pf 37 36 27 28 r3 22k w 100nf agnd 100pf c1 agnd vcm 2.2nf npo * f c = 60.3khz r5 10k w r4 13k w agnd c4 330nf c3 10 m f agnd r6 24k w ** : optional - see note p 10/18 ** 4 agnd AN930-23.eps figure 23 : low cost duplexor vi - line interface (continued) vi.1.2 - low cost daa using a 1:1 transformer a duplexor for low-cost application is proposed on figure 23. performance depends mainly on a good impedance matching with the phone line and a goodtransmit rejectionon the receiveinput(loss). a. phone line impedance matching see vi.1.1 differential duplexor. => z o = 320 w b. receive amplifier the amplifier gain g r (fixed by r5 and r7) is chosen to compensate the loss (l r ) given by the divider composed by resistor z o and transformer impedance (r s +rp ? m2), with v transmit =0 (see figure 24). the condition to make maximum line level al match with maximum codec input level a s is : application : m=1, al = 0dbm = 2.2v pp , r s +rp ? m2 = 305 w ,z o = 320 w ,l r = 0.512, a s = 1.25v pp , g r = as /(m ? al ? lr ) = 1.109 = +0.9db choosing r5 = 10k w gives r7 = 10k w and gr = 1. note : the maximum line level during v.34 commu- nication is around 1.2v pp . this gives a maximum signal level on codec output pin around 0.6v pp [1.2 ? m ? l r +g r ] that gives a good dynamic with no distortion. stlc7550 application note 15/27
r5 10k w r6 24k w zo 320 w rs 150 w rp.m2 155 w r4 14k w r7 10k w receive * ideal transformer m line ai * m lr as gr AN930-24.eps figure 24 : receive amplifier simplified ac schematic (view from line, no transmit signal) r5 10k w r6 24k w zo 320 w r4 14k w r7 10k w receive transmit signal rs rp . m 2 zline . m 2 zeq AN930-25.eps figure 25 : transmit rejection simplified ac schematic (view from transmit ampli- fier, no signal received from the line) c.transmit rejection for full duplex communication a transmit signal rejection is made on the receive amplifier by sub- tracting the v transmit signal . the loss is given by : loss = v receive v transmit ( no signal received ) [7] = 20 ? log ? ? ? z eq z eq + z o ? r5 r7 - r4 r4 + r6 ? r7 + r5 r7 ? ? ? with z eq the equivalent impedance of the phone line seen from the secondary. maximum loss is achieved when : z eq z eq + z 0 = r4 r4 + r6 ? r7 + r5 r5 application : r 5 = 10k w , r6 = 24k w , r7 = 10k w , r4 = 14k w ,z eq = 905 w ,z o = 320 w [7] = l oss = -54db (theoretical value, resistor values should be certified at 1% for good perform- ances.) vi - line interface (continued) stlc7550 application note 16/27
d. transmit filter a two-pole continuous time external filter must follow the output pin in order to remove quantiza- tion noise. the filter characteristics are : transfer function : h = v out v in = g t ? 1 1 + 2 ? x ? s + s 2 with s = j w 2 p ? f c dc gain : g t =- r3 r1 peak factor : x = 1 2 ? ? ? ? `` r 2 r 3 + `` r 3 r 2 + ``````` r 2 ? r 3 r 1 ? ? ? ` c 1 2 ? c 2 cutoff frequency : f c = 1 2 p ` r 2 ? r 3 ? c 1 ? 2 ? c 2 with f c > 2 ? f s [8] f c must be at least twice the value of the sampling frequency. the filter also amplifies (with a gain g t ) the trans- mit signal to compensate the loss (l t ) due to the divider made of resistor z o and equivalent line impedance z eq . the condition that makes the codec maximum output level a c match with maxi- mum phone line level a l is : a c ? l t ? g t = m ? a l with g t r3 r1 and l t = z line ? m 2 z o + z eq [9] for low-power application,op-amp supply is limited to 3v and can be a limitation. it is advised to use rail to rail op-amp dedicated to 3v application. op-amp should never saturate, i.e. op-amp output signal peak-to-peak level should lie within the sup- ply range : a c ? g t < 3v [10] application : dtmf level is considered as the highestlevel to be transmitted. levels used in this application are : - high group tone level is -9dbv +2/-2.5 - low group tone level is -11dbv +2.5/-2 - the level ofthe tonein thehighgroupmust be 1dbto 4db higherthan the level of the tone in the low group. in consequence,maximum dtmfsignal level is within 1.38 and 2.32v pp . maximum phone line level is set to 2.2v (corresponding to a 0dbm single tone). a l = 2.2v pp ,m=1, [9] zline = 600 w ,z eq = 905 w ,z0=320 w , l t = 0.490, a c = 2*1.25v (differential codec output), a c = 2.5v pp [9] g t =a l ? m /(a c ? l t ) = 1.796 = +5.1db choosing r3 = 22k w , (stlc7550 minimum load is 10k w ,) gives r1 = 13k w ,g t = 1.69 = +4.6db note : the maximum line level during v.34 commu- nication is around 1.2v pp . this gives a maximum signal level on codec output pin around 0.6v pp [1.2 ? m/(2 ? g t ? l t )] that gives a good dynamic with no distortion. [10] a c ? g t = 4.23v pp >3v when codec outputs are at maximum level (i.e. 1.25v pp ) the op-amp is saturated. the gain value g t is kept in order to have communication signal on codec input pin within the 0.6v range for best performances. nevertheless dtmf will be trans- mitted at a lower level, i.e. at the highest level possible without saturation that is : dtmf_level codec pin = op - amp max. output level ( 3v ) 2 ? g t in that case, dtmf signal on the phone line will be dtmf_level phone line = (op-amp maximum level (3v)) ? l t = 1.47v pp > 1.38v pp . note that dtmf level on phone line is still within the expected range, but it becomes critical for a daa designed with a l t gain not close enough to 0.5. in thecaseof critical l t gain,seenextchapterfora daa with a higher turns ratio (1:1.414 instead of 1:1). sampling frequency : 9.6khz gives f c # 19.2khz choosing r2 = 22k w , c2 = 680pf and c1 = 100pf, [8] gives f c = 19.6khz. vi - line interface (continued) z0 320 w out- out+ s t l c 7 5 5 0 r1 13k w r1 13k w r3 22k w r2 22k w r2 22k w c4 100pf f c = 19.6khz c2 680pf 37 36 * ideal transformer agnd r3 22k w agnd c1 100pf rs rp . m2 zline . m2 z eq m line * a l a c g t l t m c1 100nf AN930-26.eps figure 26 : transmit filter ac schematic stlc7550 application note 17/27
vi - line interface (continued) vi.1.3 - low cost daa using a 1.414:1 transformer for low-cost 3v daa, the transmit level can be- come critical because of the single op-amp (only 3v ofdynamic,refer to the previouschaptervi.1.2). the daa proposed on figure 27 uses a trans- former with a higher turns ratio that allows a higher transmit level on the phone line. on thisschematic, only component values and transformer reference have been changed. refer to the previous chapter for a detailed description. (vi.1.2 low cost daa using a 1:1 transformer). the calculation of the components values is given hereafter. a. phone line impedance matching the midcom 671-9366 transformer used gives the following performances : - d.c resistance : primary : 119 w 10 % secondary: 129 w 10 % - turns radio : 0.707 : 1 1 % (m = 1.414) - longitudinal balance : 46db min. - insertion loss : 2.5db max. this 0.707:1 transformer is used as a 1.414:1 one by reverting its sides : - the secondary (instead of primary) is connected to the phone line. - the primary is connected to the hybrid. the obtained transformer characteristics are : -r p = 129 w -r s =119 w - m = 0.707 zline = 600 w [1] = z o = (zline-r p ) ? m 2 -r s =116 w we take z o = 118 w b. receive amplifier m = 0.707 a l = 0dbm = 2.2v pp , r s +rp ? m2 = 184 w ,z o =118 w ,l r = 0.391 a s = 1.25v pp g r =a s /(m ? a l ? l r )= 2.05 = +6.2db choosing r5 = 20k w gives r7 = 10k w and g r =2. c. transmit rejection r5 = 20k w , r6 = 13k w , r7 = 10k w , r4 = 15k w ,z eq = 484 w ,z o =118 w [7] = loss= -66db(theoreticalvalue,resistorvalues should be certified at 1% for good performances.) d. transmit filter a l = 2.2v pp , m = 0.707 [9] zline= 600 w ,z eq = 484 w ,z0=118 w ,l t = 0.498 a c =2*1.25v (differential codec output), a c = 2.5v pp [9] g t =a l ? m /(a c ? l t ) = 1.249 = +1.9 db choosingr3 = 22k w , (stlc7549 minimum load is 10k w ,) gives r1 = 18k w ,g t = 1.22 = +1.7db [10] a c ? g t =3v pp op-amp are not saturated out- out+ in- in+ s t l c 7 5 5 0 c0 2.2nf 4.7 m f/50v phone line midcom 671-9366 zo 118 w r1 18k w r1 18k w r3 22k w r2 22k w r2 22k w 1.2k w r7 10k w c1 100pf f c = 19.6khz 100nf av dd agnd 4 8 agnd x2 ts922 pins 1-7 pins 3-5 pins 2-6 : as close as possible to stlc7550 pins * c2 680pf 37 36 27 28 r3 22k w 100nf agnd 100pf c1 agnd vcm 2.2nf npo * f c = 60.3khz r5 20k w r4 15k w agnd 330nf 10 m f agnd r6 13k w 4.7nf ** : optional - see note p 10/18 ** agnd AN930-27.eps figure 27 stlc7550 application note 18/27
vi.1.4 - low cost daa for complex impedances in the previous parts, the phone line impedance zline has been set to a resistive load of 600 w (main case). for certain countries, like germany, austra- lia, norway, sweden, u.k., or in the new european standard tbr21, zline is considered as a r,r,c network. this part gives an example based on a low cost daa for tbr21 complex impedance: z tbr21 = 270 w + (750 w //150nf) it can used as a universal r, r, c network that match with any complex impedance countries as it provides optimum return loss (min. 16db, see fig- ure 28). country z=r l1 +(r l2 //c l ) r l1 ( w ) r l2 ( w ) c l (nf) min. return loss required (db) germany 220 820 115 18 australia 220 820 120 14 norway 120 820 110 9 sweden 275 850 150 18 united kingdom 370 620 310 14 refer to section vi.1.2 for a general description of the low cost daa. switching from real to complex impedances re- quires to review the impedance matching and the transmit rejection parts. vi - line interface (continued) r10 c9 r9 rs rp m rl2 rl1 cl ring zline equivalent to zline r9 = rl2 x m 2 r10 = (rl1 - rp) x m 2 -rs c9 = cl/m 2 AN930-29.eps figure 29 a. phone line impedance matching on a specific complex impedance figure 29 shows the equivalent model of a line interface, where rp and rs are the transformer resistances, and zline the phone r,r,c complex impedance. r10, r9, c9 are shown on the daa schematic given in figure 30. impedancesare matching when daa input imped- ance (composed of r9,c9,r10,rs and rp) is equivalent to line impedance zline. it gives : r9 = rl2 . m 2 , c9 = cl/m 2 r10 + rs + rp.m 2 = rl1.m 2 note that the transformer equivalent resistance (rs+rp.m 2 ) must be lower or equal to rl1.m 2 . application this example is targeted for tbr21 impedance: r l1 = 270 w ,r l2 = 750 w ,c l = 150nf. the transformer midcom 671-8332 used in pre- vious schematics present an equivalent resistor (rs + rp . m 2 ) too high. it is replaced by a mid- com 671-8248 that gives the following perform- ances : rs = 67.5 w , rp = 67.5 w , m=1 rs + rp . m2 =135 < rl1 then r9 = 750 w , r10 = 130 w , c9 = 147nf (100nf +47nf). it gives a return loss around 30db in the whole bandwidth. 10 20 30 40 50 60 10 2 10 3 10 4 return loss f (hz) 300 3.4k 16 26 24 14db germany/australia united kingdom sweden norway 20 . log z+z tbr21 z-z tbr21 AN930-28.eps figure 28 stlc7550 application note 19/27
out- out+ in- in+ s t l c 7 5 5 0 midcom 671-8248 r1 13k w r1 13k w r3 22k w r2 22k w r2 22k w r11 1.2k w r7 10k w c1 100pf 100nf av dd agnd 4 8 ts922 pins 1-7 pins 3-5 pins 2-6 c2 680pf 37 36 27 28 r3 22k w c1 100pf v cm c7 2.2nf r5 10k w r4 43k w agnd c4 220nf r6 13k w r8 51k w c8 1nf c5 100nf v cm r9 750 w c9 147nf c3 10 m f r10 130 w c6 2.2nf rs 67.5 w rp 67.5 w tx1 rl1 270 w rl2 750 w cl 150nf zline agnd agnd v line v 2 v transmit v 1 agnd a n930-30.eps figure 30 vi - line interface (continued) vi.1.4 - low cost daa for complex impedances (continued) b. transmit rejection transmit rejection performance is directly linked to the line impedance. with complex impedance lines, transmit rejection needs to be featuredwith a complex network (com- posed of r6,r8,c8 and r4) in order to follow the line impedance move within the whole bandwidth. r4 is set to a convenient value (r4 = 43k w ). note that capacitor c4 becomes critical for a good rejec- tionat low frequencies.it is so interestingto choose r4 high enough to obtain a good r4,c4 cut-off frequency with a low cost c4. detailed calculation are given below for any com- plex impedance value. in this example, r5 is chosen equal to r7 (r5 = r7 = 10k w , refer to the chapter ob. receive amplifiero, page 15). transmit rejection is achieved when v1 = 1/2 ? v2 in the whole bandwidth. - at high frequencies, r9, rl2 and r8 have no influence (shunted by capacitors c9, cl and c8). taking r9 = rl2 = r8 = 0, it givesv2 = vtransmit andthenv1 =1/2vtransmit. then r6 = r4 = 43k w . - atlowfrequencies,c9,clandc8havenoinfluence. transmitrejection canbe calculatedconsideringonly resistors. v2 v transmit = r10 + rs +( rp + rl1 + rl2 ) ? m 2 r9 + r10 + rs +( rp + rl1 + rl2 ) ? m 2 = rl1 + rl2 / 2 rl1 + rl2 = 0.632 v1 = 1 2 ? v2 = 0.316 r8 + r6 = 1 - 0.316 0.316 ? r4 = 93k w r8 = 93k w , r6 = 51k w values should be certified at 1% for good per- formances. c8 = rl1 ? rl2 ( rl1 + rl2 / 2 ) ? r8 ? cl = 923pf we take c8 = 1nf. note : capacitorc9 and related resistors constitute a low-pass filter for phone line incoming signals. we have to check that its cut-off frequency is outside the bandwidth : fc9 = r9 + req 2 p ? r9 ? req ? c9 with req = r10 + rs + m 2 .rp fc9 = 5.3khz, then the low-pass filter has no effect in the bandwidth. stlc7550 application note 20/27
experimental measures gives an electrical receive echo in the same range (+3db higher) than for 600 w lines (refer to figure 46, page 27). detailed calculation (see figure 31) transmit rejection is achieved when v1 = r5 r7 + r5 ? v2 [1] v2 v transmit = al ? 1 + j w w l1 1 + j w w l2 with al = rl1 + rl2 /2 rl1 + rl2 w l1 = rl1 + rl2 / 2 rl1 ? rl2 ? cl , w l2 = rl1 + rl2 rl1 ? rl2 ? cl w l1 < w l2 v1 v transmit = ar ? 1 + j w w r1 1 + j w w r2 with ar = r4 r4 + r8 + r6 w r1 = 1 r8 ? c8 , w r2 = r4 + r6 + r8 r8 ? ( r4 + r6 ) ? c8 w r1 < w r2 solving equation [1] , gives ar = r5 r5 + r7 ? al with w r1 = w l1 and w r2 = w l2 it gives the following component values r6 + r8 = r5 ? ( 1 - al )+ r7 al ? r5 ? r4 ,r6 = r7 r5 ? r4 c8 = rl1 ? rl2 ( rl1 + rl2/2 ) ? r8 ? cl vi - line interface (continued) complex impedance r l1 ,r l2 ,c l choice of a convenient transformer rs + rp . m2 > r l1 .m2 impedance matching r9 = r l2 .m2 c9 = c l /m2 r10 = (r l1 - rp) . m2 - rs choice of a convenient r4 value r6 = r7/r5 . r4 al = r l1 +r l2 /2 r l1 +r l2 c8 = r l1 .r l2 (r l1 +r l2 /2).r8 c l r8 = r5 . (1 - al) + r7 al . r5 .r4 - r6 f c9 = r9 + req 2 . pi . r9 . req . c9 > 4khz ? req = r10 + rs + rp . m2 f c9 checking AN930-31.eps figure 31 stlc7550 application note 21/27
r1 20k w bsp52 r3 22 w 0.5w c2 10 m f r2 12k w req = r3 (1 + r1 r2 ) AN930-32.eps figure 32 : current driver block vi - line interface (continued) vi.2 - current driver the current driver block provides the dc current required to maintain the line in a off-hook condition. it mustprovidea high ac impedancetoavoidattenu- ating the phone signals. this is achieved by using a darlington device or 2 npn transistors that looks resistive for dc current and gives a high ac imped- ance across tip and ring within the voice band. dc current is fixed by the equivalent resistor r eq , depending on the phone line characteristics of the country to which the modem is dedicated (minimum current required,maximum current and line voltage). application : r eq =58 w c1 10nf til 127 4.7k w av ddm 10k w c2 0.47 m f high voltage d3 1n4148 d1 15v d2 15v agnd ring detect tip ring 0.5w 680k w AN930-33.eps figure 33 : ring detect tsi270b1 1 8 phone line to current drive block tip ring line+ line- 57 tsi270b1 features : single device providing diode bridge bidirectional protection crowbar protection peak pulse current : i pp = 30a, 10/1000 m s voltage : 270v maximum current : i o = 0.5a a n930-34.e ps figure 34 : modem protection 10k w 100k w av dd off-hook line + tip daa tx2-5v phone socket AN930-35.eps figure 35 : hook switch vi.2.1 - ring detect (see figure 33) vi.2.2 - protection devices the bridge protects modem against tip and ring inverting. the protection block is varistors that protect modemagainstspikes(e.g. lightning).thetwo protec- tion devices are included in a unique component tsi270b1. the connections are shown on figure 34. vi.2.3 - hook switch the hook switch connects the pstn to the daaor to the phone socket. to answer an incoming call, the system needs to makethe connectionon the pstnafteraringingunit. the diode is used to bypass current peak at the hook switch pins during switching. stlc7550 application note 22/27
r7 22k w c3 680pf r8 13k w 17 41 42 4 3 38 16 15 14 39 40 8 9 mcm m/s din dout fs sclk reset pwrdwn hc0 hc1 ts tstd1 xtalout xtalin 7 19 30 18 28 27 26 25 37 v refn v cm v refp in- in+ auxin- auxin+ out- 36 out+ 29 5 dv dd av dd 62031 dgnd agnd1 agnd2 13k w r6 22k w 22k w 22k w c4 2.2nf c6 2.2nf npo * 10k w r3 v cm 1.2k w r5 10k w 10 m f * 100nf * 100nf * 100nf * 10 m f* 36.864mhz cl = 10pf 27pf 10nf 10pf dgnd dgnd 1.2 m h to digital controller av dd 100nf dgnd 22 m f * * av dd 100nf dgnd 22 m f * * av dd analog ground plane digital ground plane as close as possible to the pin. * r9 20k w stlc7550 10 m f* optional (see note page 10/22). ** 22 m f 22 m f 10 m f 13k w 24k w 330nf 100nf 100pf 100pf 100nf av dd agnd 4 8 agnd ts922 x2 pins 1-7 pins 3-5 pins 2-6 r14 10k w av dd r15 100k w off hook ++ 10 m f 12k w ** r12 0.47 m f 15v 15v mmbz5254 til127 av dd ring c7 10nf 4.7k w r13 680k w 10k w 250v 10 w phone wall 5 7 8 1 22 w 0.5w agnd AN930-37.eps figure 37 : appendix : suggested implementation vii - application cpu, microcontroller stlc7550 daa 4 3 16 41 42 27 28 36 37 fs sclk din dout pwrdwin out+ out- in+ in- 3v reset off-hook ring pstn AN930-36.eps figure 36 : low power host processing modem application using stlc7550. stlc7550 application note 23/27
AN930-38.pcx figure 38 : signal to noise ratio : adc AN930-39.pcx figure 39 : signal to noise ratio : adc + dac viii - performances the measurements have been performed with a rodhe & schwarz audio analyzer2hz-300khz upd. the sampling frequency is 9.6khz and over- sampling ratio is 160. viii.1 - adc converter the sndr measured is 83db for a signal level equal to -3dbr (see figure 38). figure 39 givesthe sndr fortheanalog todigital/digi- tal to analog loop back. we can see that the sndr is 78db at -6dbr and this value is 80db at -3dbr. in this configurationthe noise power of the adc and the dac are added conducting to a +3db noise powerincrease.so it meansthat bothadcand dac present a sndr to 83db for a -3dbr signal level. dynamic range : dr the measurementresult is 87.5db for a signal level equal to -20dbfs (0.0884v rms ) (see figure 40). the dr figure is dependant on the oversampling ratio and the supply voltage : see below table. v dd 3v 5v over 64 80db 78db 160 87.5db 85db total harmonic distortion the thd measured with a -6dbfs signal level is 93db (see figure 41). offset adc offset is specified within the range 300lsb. it is recommended to perform offset cancellation at the dsp side. viii.2 - dac converter figure 42 gives the measurement result of the dynamicrange. the signal level is -20dbr.dynamic range extrapolated to full range is 87db. the total harmonic distortion (harmonic frequen- cies in the band 100hz-4080hz) is equal to -94db (see figure 43). stlc7550 application note 24/27
AN930-40.pcx figure 40 : dynamic range. supply = 3v, oversampling ratio = 160. viii - performances (continued) AN930-41.pcx figure 41 : total harmonic distortion AN930-42.pcx figure 42 : dac (dr = 87db, level = -20dbr) stlc7550 application note 25/27
AN930-43.pcx figure 43 : dac (thd = -93db, level = -6dbr) viii.3 - daa characteristics dc mask figure 44 gives the tip and ring voltage versus the line current. the slopeand the absolutevoltage are managed with the resistor r1, r2 and r3 (see figure 32) in order to fulfill the different countries regulation. return loss figure 45 gives the 600 w impedance matching in single ended configuration. the low frequency re- sponseis significantly dependanton the c3 capaci- tor value (see figure 23). the return loss figure is stable over a 15 to 120ma line current range. 20 40 60 80 100 0 5 11 10 9 8 7 6 dc voltage (v) phone line current (ma) a n930-44.e ps figure 44 012345 frequency (khz) return loss (db) 40 30 20 c3 = 22 m f c3 = 10 m f AN930-45.eps figure 45 viii - performances (continued) stlc7550 application note 26/27
electrical receive echo (single ended duplexer mode) figure 46 gives signallevels at differentsuccessive points of the transmit channel. the signal level at the transmit stlc7550 outputs is -6dbr (0dbr = 2.5v pp ). the external duplexer transmit gain (+4.6db) com- pensates part of the transformer stage losses and lead to a global attenuation from the stlc7550 and the line of about -2db. the electrical echo is measured at the in+/- inputs for a 600 w resistive line impedance. the two plots corresponding to different c4 (see figure 22) ca- pacitor values show the low frequency rejection difference. 012345 frequency (khz) 0 -20 -10 -30 -40 -50 -60 -70 signal level (dbv) v out +/- v line v in +/- c4 = 330nf c4 = 1 m f AN930-46.eps figure 46 : transmit single ended mode information furni shed is believed to be accurate and reliable. however, sgs-thomson micr oelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no licence is granted by implication or otherwise und erany patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without notice. this pu blication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1998 sgs-thomson microelectronics - all rights reserved purchase of i 2 c components of sgs-thomson microelectronics, conveys a license under the philips i 2 c patent. rights to use these components in a i 2 c system, is granted provided that the system conforms to the i 2 c standard specifications as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - morocco the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. viii - performances (continued) stlc7550 application note 27/27

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